Conventionally, a LDMOS (laterally diffused metal oxide semiconductor) transistor and a IGBT (insulated gate bipolar transistor) are well known as a power semiconductor device for large current. It is necessary for the semiconductor device to secure a withstand voltage (i.e., L load tolerance) with respect to a reverse electromotive force, which is applied in a case where a L load such as a coil is connected. Specifically, the semiconductor device generates heat when the device functions. Thus, a parasite bipolar operation may be easily induced, and the L load tolerance may be reduced easily. A technique for restricting the reduction of the L load tolerance in the semiconductor device is, for example, disclosed in JP-A-2005-243832.
JP-A-2005-243832 teaches a LDMOS transistor such that an impurity concentration near a drain cell (as a drift layer) through a base layer is set to be high impurity concentration so that the L load tolerance for practical use is secured. Further, in the LDMOS transistor, the width of the base layer is in a range between 1.0 micrometers and 1.4 micrometers.
In the LDMOS disclosed in JP-A-2005-243832, the L load tolerance is improved. However, since the impurity concentration near the drift layer through the base layer is increased, the on-state resistance is largely increased in contrast with the improvement of the withstand voltage. Further, it is necessary to design the width of the base layer within a certain range, which is comparatively limited. Thus, a design of the semiconductor device and the manufacturing method are restricted. Thus, another technique is required.